Pick your data converter
Choose ADC or DAC, the silicon vendor, the part, and the JESD generation. The model list updates automatically based on the supported generation.
Pick your FPGA platform
Choose the FPGA vendor, family and target device. Lane-rate feasibility is verified later against this family's transceiver capability.
The configurator is in beta. AMD Xilinx is live: 7-series and Zynq-7000 (Spartan-7, Artix-7, Kintex-7, Virtex-7, Zynq-7000) plus UltraScale+ (Kintex, Spartan, Zynq, and Zynq UltraScale+ RFSoC). Intel Altera follows release by release. Devices are reviewed and added continuously. If your part is missing, ping us via the contact page and we will scope an addition.
Set link parameters
Sample rate, lane count, subclass and latency mode. Lane rate is computed live and checked against the FPGA family's transceiver capability.
Submit your configuration
Our engineering team will review your build request and respond with a tailored proposal.
Configuration summary
Your contact
Your request has been sent to engineering.
We have your configuration. Our engineering team will review and reply to with a tailored proposal, typically within 1–2 business days.
Configuration code
Save this code. Paste it back into the configurator at any time (top right of the configurator) to restore the exact same setup. Quote it in any follow-up email and we will know exactly which configuration you are referring to.
The configurator is in beta. We work hand-in-hand with first customers to make every build a clean fit for their hardware. You will get a usable solution and direct engineering attention while we refine the platform. Self-service download of the trial package is planned for a future release.
What happens next
- Our engineering team reviews your configuration.
- We respond with a tailored proposal, typically within 1–2 business days.
- If anything needs clarification, we schedule a brief technical alignment call.
- We deliver the trial bitstream and reference design package.