- Up to 4 lanes
- Time-limited bitstream
- Out-of-the-box reference design
- Transceiver clocking
- Integrated logic analyzer with waveform view
- Public docs & quick-start guide
- Production deployment
- System-level clocking topology
- Engineering support
- Full lane count
- Synthesizable RTL package
- Full timing constraints (XDC / SDC)
- System-level clocking topology
- Integration documentation
- Email support during integration
- Bug-fix updates for the licensed build
- Bring-up consulting
- Clocking validation
- Device-specific configuration
- Board-specific tuning
- Direct access to senior engineering
- On-site workshops (optional)
Common questions
Can I evaluate on a real board with the trial?
Yes. The trial bitstream runs on real hardware (evaluation board or your own board) and is time-limited but otherwise fully functional. The JESD204 link comes up, samples flow, and the integrated logic analyzer lets you probe the link directly in the Vivado or Quartus hardware manager. You see live link state, sync, lane alignment and sample data on screen. When you are ready to remove the time limit and unlock the full lane count, contact us for a Production licence.
How is the production licence calculated?
Per project. The price scales with the target platform and the lane count. The platform covers the FPGA family, the JESD generation, the ADC/DAC silicon and the hardware board (evaluation board or custom hardware). The hardware board is typically the most crucial factor. We send a fixed quote within 1–2 business days after a short technical alignment.
Do I get the source RTL?
No. The Production package ships as IEEE-1735 encrypted RTL, the industry-standard delivery format for paid FPGA IP. Vivado and Quartus consume it transparently for synthesis, place-and-route, and simulation. You keep your existing build environment and remain in full control of the surrounding design. The core itself is opaque; everything you build around it is yours.
Are updates included?
Bug-fix updates for the licensed configuration are included. Major feature releases (e.g., new converter families) are scoped separately.
Is the licence per device or per design?
Per design / per project. One licence covers a configuration deployed across the units of a single product or revision. Multi-product or multi-revision deals are available.
What about the service layer, when do I need it?
If your team has limited prior FPGA + clocking experience, a few hours of senior engineering up front typically save weeks of bring-up. Optional, never required.
Ready to talk numbers?
Tell us your converter, your FPGA, and your timeline. We will reply with a fixed-price proposal.