§1 The JESD204 family at a glance

JESD204 is a serialised, point-to-point interface between high-speed data converters (ADCs and DACs) and logic devices such as FPGAs, ASICs and DSPs. It replaces the bulky parallel LVDS or CMOS busses of earlier generations with a small number of multi-Gbps differential lanes, which is what makes RF-rate sampling feasible in modern instrumentation, 5G fronthaul, software-defined radio and phased-array radar.

The standard is published by JEDEC. Five revisions have been released so far:

1. JESD204
   April 2006
   Single lane, single converter. Up to 3.125 Gbps. Foundation document.
2. JESD204A
   April 2008
   Multi-lane and multi-converter support. No deterministic latency.
3. JESD204B
   July 2011
   Up to 12.5 Gbps per lane. 8B/10B encoding. Three subclasses, ILAS, LMFC, CML drivers. Most widely deployed revision today.
4. JESD204C
   December 2017
   Up to 32.45 Gbps per lane. Adds 64B/66B and 64B/80B link layers. Mandatory scrambling on the new link layers, optional Fire-code FEC, JCOM PHY metric. Errata revision JESD204C.01 followed in December 2021.
5. JESD204D
   December 2023
   PAM4 signalling at up to 116 Gbps (NRZ retained at up to 58 Gbps). Mandatory Reed-Solomon FEC for PAM4. New Subclass 3 (MULTIREF), Subclass 2 removed. Three reach classes (XSR / MR / LR). Transport layer backward compatible with B and C, the RS-FEC link layer is not.

Why a serialised interface in the first place

An n-bit parallel interface needs roughly 2n+ pins (data + clock + control), and at GSPS rates the skew between those pins becomes the dominant design problem. JESD204 trades pin count for line rate: a 12-bit, 5-GSPS ADC over JESD204B might run on 8 lanes at ~7.5 Gbps each instead of 24+ pins of LVDS, with the receiver responsible for re-aligning and re-assembling samples. The resulting board area, routing complexity, and connector pin count drop dramatically, and the link rate scales with FPGA SerDes capability instead of with package size.

§2 JESD204B vs JESD204C

B and C are the two revisions that matter for most current designs. C is a strict superset feature-wise but B remains common on shipping silicon. The configurator supports both. Pick based on lane-rate need, on what the converter actually offers, and on the FPGA family's transceiver capability.

Which one for which application

• JESD204B is fine when your converter and FPGA both support it and your aggregate sample throughput stays inside the 12.5 Gbps-per-lane envelope. It's the most mature implementation in vendor silicon and the easiest to bring up.
• JESD204C in 8B/10B mode is the recommended bring-up path on JESD204C-capable devices, because the data-link layer is unchanged from B. Switch to 64B/66B once the link is stable.
• JESD204C in 64B/66B mode is the long-term target for new high-rate designs: 3.125% coding overhead instead of 20%, mandatory scrambling for EMI, and FEC available when the channel needs it.
• 64B/80B exists mainly to let vendors reuse 8B/10B clocking ratios while still gaining the new sync structure and FEC; it is rare in customer designs.

§3 Subclasses & deterministic latency

A JESD204 system's subclass determines how the receiver and transmitter agree on a common timing reference, and therefore whether the link end-to-end latency is fixed across resets, power cycles and device-to-device manufacturing variation. Deterministic latency matters whenever multiple converters need to be sample-aligned (multi-channel receivers, beamforming) or whenever the digital processing chain has a deadline (DPD loops, AGC, MRI gradient sequencing).

When you actually need deterministic latency

You need it when downstream processing depends on a fixed time-of-flight from the analog front-end. Common cases:

• Digital pre-distortion (DPD) loops in transmitters. The DPD update loop closes at multi-MHz rates and is sensitive to changes in feedback latency.
• Automatic gain control (AGC) loops in receivers, for the same reason.
• Multi-antenna phased arrays. Beamforming requires sample alignment across elements; latency drift between elements destroys the beam.
• MRI gradient and RF chains. Sequence timing is bounded by deterministic deadlines.
• Multi-instrument synchronisation. Trigger-aligned data acquisition across a chassis or across multiple chassis.

If your application is single-channel data capture, a software-defined radio without beamforming, or a logger, you almost certainly don't need it. Subclass 0 is fine and bring-up is faster.

§4 The four protocol layers

JESD204 is organised as four stacked layers. Each has a separate clock domain and a separate concern. Knowing which layer a problem lives in is the most useful debugging skill for the standard.

§5 Lane rate math

The per-lane line rate of a JESD204 link is determined by the number of converters per device, the resolution per sample, the sample rate, the lane count and the line-coding overhead. The simplified formula:

lane_rate = (M × N' × fs / L) × line_coding

where
  M    = converters per device
  N'   = round_up(N, 4)        bits per sample including alignment bits
  fs   = sample rate in samples/second
  L    = number of lanes
  line_coding = 10/8   for JESD204B (8B/10B)
              = 66/64  for JESD204C 64B/66B
              = 80/64  for JESD204C 64B/80B

Worked example

A quad-channel 14-bit ADC link on AMD Xilinx Kintex UltraScale+:

Converter:  TI ADS54J54  (M = 4, N = 14)
JESD:       JESD204B (8B/10B)
fs:         500 MSPS
Lanes:      L = 8
N':         round_up(14, 4) = 16

lane_rate = (4 × 16 × 500e6 / 8) × 10/8
          = 4 GHz × 1.25
          = 5 Gbps  per lane

Kintex US+ transceiver ceiling: 16.375 Gbps  →  feasible

Halving the lane count to L = 4 doubles the per-lane rate to 10 Gbps, still within Kintex UltraScale+. Dropping to L = 2 pushes it to 20 Gbps, beyond the Kintex US+ ceiling (16.375 Gbps), so you would move to a higher-grade family such as Virtex UltraScale+ (28.21 Gbps) or Versal AI Edge (32.75 Gbps).

Per-family transceiver ceilings

The configurator validates the lane rate against these ceilings. Approximate values; vendor data sheets are authoritative:

§6 Quick start: from spec to trial JESD204 build request

A walk-through of the configurator. We will configure a typical RF ADC link on AMD Xilinx Kintex UltraScale+ and request a trial RTL package.

1 · Pick your converter

Open the configurator. Select ADC as the type. Pick Texas Instruments as the vendor and ADC12DJ5200RF as the model. Choose JESD204B.

The platform surfaces the device's sample rate (5.2 GSPS per channel in dual-channel mode, 10.4 GSPS in single-channel mode) and resolution (12-bit) as a sanity check.

2 · Pick your FPGA

Pick AMD Xilinx, then Kintex UltraScale+, then a target device such as XCKU15P. The family transceiver capability (16.375 Gbps per lane) is loaded for the next step's feasibility check.

3 · Set link parameters

Suppose the application uses 5 GSPS per channel over 16 lanes for a Subclass 1 deterministic-latency receive chain. Enter 5000 MSPS and 16 lanes. The configurator computes the lane rate live and flags feasible or exceeds family limit.

4 · Generate the trial

Click Generate trial build. The platform produces a manifest with the RTL files, timing constraints, clocking topology TCL, and an integration guide. For this MVP, downloads are issued after a short technical alignment, and the button starts that conversation. Once you are ready to ship, click Request production licence for a fixed-price quote.

§7 Glossary

Definitions follow the canonical JEDEC convention and the Analog Devices JESD204 reference glossary. Symbols and parameter names are normative.

Control characters (8B/10B link layer)

Abbreviations

CGS

Code Group Synchronisation. The 8B/10B link-layer state in which the receiver locks onto the /K/ K28.5 character stream sent by the transmitter prior to ILAS.

ILAS

Initial Lane Alignment Sequence. The four-multiframe training sequence following CGS in 8B/10B bring-up; carries the link configuration and aligns lanes across the link.

LMFC

Local Multiframe Clock. Per-device divider that defines the multiframe boundary. Reset by SYSREF in Subclass 1, by SYNC~ in Subclass 2.

LEMC

Local Extended Multiblock Clock. The 64B/66B-mode equivalent of LMFC; defines the boundary of an Extended Multiblock.

MCDA

Multiple-Converter Device Alignment. Alignment of converter samples across multiple converter devices on the same link.

MCDA-ML

MCDA Multiple-Lane. Alignment across both multiple converters and multiple lanes per converter.

NMCDA

No Multiple-Converter Device Alignment. Mode in which converter alignment is not maintained across devices.

RBD

RX Buffer Delay. Receiver-side elastic buffer delay in frame clocks, used to absorb lane-to-lane skew while preserving deterministic latency.

EMB

Extended Multiblock. The 64B/66B-mode super-structure of E multiblocks (each 32 blocks, each 66 bits) that replaces the JESD204B multiframe.

EoMB

End-of-Multiblock sequence (binary 00001) carried in the sync-bit channel.

EoEMB

End-of-Extended-Multiblock identifier bit; signals the boundary between successive EMBs.

CDR

Clock and Data Recovery. Receiver-side circuitry that extracts the bit clock from the serial data stream, relying on transition density guaranteed by 8B/10B encoding or by mandatory scrambling of 64B/66B.

CML

Current-Mode Logic. The differential output stage used by all JESD204 PHY drivers; replaces the LVDS or CMOS interfaces of earlier converters.

FEC

Forward Error Correction. Optional in JESD204C (Fire code), mandatory in JESD204D for PAM4 (Reed-Solomon).

CRC

Cyclic Redundancy Check. CRC-3 or CRC-12 carried in the JESD204C 64B/66B sync-bit channel; replaced by the RS-FEC error-detection role in JESD204D.

JCOM

JESD204 Channel Operating Margin. The PHY-compliance metric introduced with JESD204C Class C PHY, supplementing the eye-mask compliance of Class B PHY.

FMC

FPGA Mezzanine Card (VITA 57.1). A common physical form factor for JESD204B/C ADC and DAC daughter cards.

SerDes

Serialiser/Deserialiser. The transceiver hard macro (Xilinx GTX/GTH/GTY, Intel Arria/Stratix transceivers) that implements the JESD204 physical layer.

NRZ / PAM2

Non-Return-to-Zero, two-level Pulse Amplitude Modulation. Used by JESD204B and JESD204C, retained as the legacy mode of JESD204D.

PAM4

Four-level Pulse Amplitude Modulation. New in JESD204D; raises the per-lane line rate to 116 Gbps but has a higher raw bit-error rate that mandates RS-FEC.

XSR / MR / LR

Extra-Short-Reach / Medium-Reach / Long-Reach. The three channel-reach classes defined in JESD204D.

MULTIREF

The JESD204D Subclass 3 multi-device alignment mechanism that uses a Local Alignment Clock instead of SYSREF; provides alignment but not deterministic latency.

Link parameters (transport-layer configuration)

L

Lane Count. Number of serial lanes on the link.

M

Converter Count. Number of converters per device.

F

Octets per Frame per Lane.

S

Samples per Converter per Frame.

N

Converter Resolution. Effective number of bits per sample.

N'

Total bits per sample. N rounded up to the nearest nibble (4-bit) boundary, plus optional control (CS) or tail (T) bits, so N' = N + CS + T. Often set to 16 in practice for 8- to 16-bit transceiver commonality.

K

Frames per Multiframe (8B/10B mode).

HD

High-Density user data format. Permits a sample to span the boundary between two octets; relaxes alignment but complicates framing.

E

Number of multiblocks in an Extended Multiblock (64B/66B mode).

SCR

Scrambling enable flag (0 = disabled, 1 = enabled). Optional in JESD204B; mandatory for JESD204C 64B/66B and 64B/80B.

CF / CS

Control Words per Frame Clock cycle / Control bits per sample.

P

(JESD204D) Number of payload octets in one FEC code word.

Clocks

Character clock

Clock with which 8B/10B characters and octets are generated.

Conversion clock

Clock used by a converter device to perform the A/D or D/A conversion. Equals the converter's sample rate.

Link clock

Link parallel clock feeding the link layer. For JESD204B: lane rate divided by 40 or 80. For JESD204C 64B/66B: lane rate divided by 66.

Device clock

Master clock supplied to the JESD204 device, from which all other clocks must be derived.

Frame clock

Clock rate at which samples are generated or processed. Equal to the conversion clock except for interpolating/decimating DACs and ADCs, where it is slower by the interpolation/decimation factor.

Line clock

Clock for the high-speed serial interface (the serial bit rate).

Local clock

A clock generated inside a JESD204 device.

SYSREF

Slow source-synchronous clock used to reset device-clock dividers (including LMFC) and thereby achieve deterministic latency in Subclass 1. May be one-shot, gapped-periodic or periodic. When present, SYSREF is the master timing reference of a JESD204B/C system.

SYNC~

System-synchronous, active-low signal from the receiver to the transmitter. Used in Subclass 2 for deterministic latency (vendor guideline: below approximately 500 MSPS), and in 8B/10B mode for synchronisation handshakes generally. Synchronous to the LMFC.

§8 Further reading

A curated reading list. Most vendor literature is freely downloadable; JEDEC standards require free registration but are then licensed material.

Standards (JEDEC)

• JESD204D · JEDEC, December 2023 · current revision, PAM4, RS-FEC, Subclass 3
• JESD204C.01 · JEDEC, December 2021 · errata revision of C, canonical reference for new C designs
• JESD204C · JEDEC, December 2017 · introduces 64B/66B and 64B/80B
• JESD204B · JEDEC, July 2011 · the most-deployed revision

Vendor primers (must-reads)

• JESD204B Survival Guide · J. Harris, ADI 2013 · the de-facto first read for JESD204B engineers
• Demystifying Deterministic Latency Within JESD204B Converters · I. Beavers, ADI MS-2626, 2014
• JESD204B Subclasses, Part 1: An Introduction to JESD204B Subclasses and Deterministic Latency · ADI Technical Article
• JESD204B Subclasses, Part 2: Subclass 1 vs. Subclass 2 System Considerations · ADI Technical Article MS-2677
• Quickly Implement JESD204B on a Xilinx FPGA · H. Sun, Analog Dialogue 49, 2015
• JESD204C Primer, Part 1 · D. Jones, ADI 2018
• JESD204C Primer, Part 2 · D. Jones, ADI 2018
• TI SBAA517: What to Know About the Differences Between JESD204B and JESD204C · TI 2020 · clean side-by-side
• TI SLYY057: Ready to Make the Jump to JESD204B? · TI 2018
• TI SBAA221: Implementing JESD204B SYSREF and Deterministic Latency with the ADC32RF45 · TI 2017

Open-source JESD204B IP

• ListenToJESD204B · Bhattacharjee et al., arXiv 2025 · lightweight Subclass 1 receiver, SystemVerilog, Solderpad 0.51
• LiteJESD204B · EnjoyDigital · Migen/LiteX-based, supports 7-Series, UltraScale and ECP5
• ADI JESD204 HDL Framework · GPL-2 / commercial dual-licence reference implementation

Academic

• A JESD204B-Compliant Architecture for Remote and Deterministic-Latency Operation · Bellato et al., IEEE TNS 2017 · remote-ADC over deterministic-latency serial link
• Hardware Acceleration of Digital Pulse Shape Analysis Using FPGAs · Balcells-Ventura et al., Sensors 2024 · JESD204B in nuclear-physics instrumentation, Zynq UltraScale+ MPSoC

A more comprehensive bibliography (43 entries, IEEE-style citations, Rev. 1.1, July 2026) is available as a PDF: ↓ JESD204_Bibliography_IEEE.pdf